Choosing Destiny Research Paper Throughout Life Essay Sample For College

Life

Choosing Destiny Essay, Research Paper

Throughout life, one will meet many ups, downs, highs and depressions. It ’ s rather obvious that some will manage the downs and depressions better than others. These jobs can run anyplace from something serious such as household struggles, or it may be something foolish like laundry issues. Others find that their depressions in life are due to the fact that they face the same day-to-day obstructions, and tend to acquire annoyed with the repeat behind them. Life all of a sudden seems to hold no peculiar significance, and a individual begins to experience worthless. Life in itself is insistent, nevertheless a individual can merely take so much until they begin to necessitate a serious alteration.

The construct stated above is demonstrated in A Jest of God by Margaret Laurence and The Book of Eve by Constance Beresford-Howe. In A Jest of God, Rachel is deprived of a fulfilling life style chiefly because of the bounds she is placed under by her female parent. Day in, and twenty-four hours out, Rachel is populating a confined life and feels there is no possibility of altering it. Her sister Stacey has married and moved off and Rachel is the lone support her female parent has. Rachel feels obliged to supply and care for her. After her matter with Nick Kazlik, Rachel begins to hold a different mentality on life and hence decides to alter it drastically. In The Book of Eve, Eve is restricted to some of life ’ s simple things such as traveling out for walks. Her hubby Burt is afraid of fire and resents being left entirely even for short intervals. After Eva decides to go forth, she experiences a whole new life style. Eva now has adequate clip to travel out for ambles, ’ store ’ , and is still left with excessively much clip in which to contemplate her state of affairs. In each novel it ’ s evident that the supporters are acquiring fed up with their lives and are taking affairs into their ain custodies.

In A Jest of God the supporter is Rachel, a thin, tall, gangling instructor in the town of Manawaka. Rachel lives with, supports and attentions for her female parent despite her slightly negative feelings towards her. Rachel ’ s sister Stacey does non care to see her female parent, and clearly does non hold any purposes of go toing to her medical demands. Therefore, Rachel is left with an terribly annoying female parent who criticizes and controls her life wherever, and whenever she gets the chance to make so. At the age of thirty-four, Rachel is single and populating with her female parent. Her life revolves chiefly around her class one category at the school she teaches, and her fantastic female parent. She doesn ’ t precisely associate with many people except for Calla, a instructor at her school and Willard Sidley, the principal of the establishment.

Rachel seldom goes out except for the occasional film with Calla. Calla frequents a local Tabernacle, and rather frequently invites Rachel to travel along. However, she does non experience comfy go toing such a topographic point and seldom agrees to traveling. Willard besides invites Rachel to dinner with his married woman and a friend, but Rachel doesn ’ t needfully appreciate their company and declines the offer. As a consequence of her ordinary life, Rachel begins to hanker for something different, peculiarly a hubby.

The individual to thank for Rachel ’ s alteration is Nick Klazik. He comes into her life as a aftermath up call! As Rachel ’ s sexual matter with Nick becomes more intense, the reader notices a important alteration in Rachel ’ s mentality on life. Until Nick came along, she kept more to herself and thought of nil more than populating a twenty-four hours to twenty-four hours low life. However, Nick brought out the best in her and it ’ s clear that Rachel ’ s thoughts about her hereafter Begin to alter drastically, peculiarly sing kids. Rachel references rather frequently her surveies of babes and their female parents. Rachel will talk of a babe and automatically give mention to a book she read sing the same subject. For the first clip, Rachel feels loved and begins to see matrimony and a household. For Rachel, the lone household she has is her female parent. She has no sense of holding something of her ‘ ain ’ , such as a hubby and kids. Nick has been the alteration in Rachel ’ s life. He was the 1 responsible for taking Rachel out of her day-to-day modus operandis. Nick was the beginning of amusement for Rachel.

Rachel changed chiefly after her close brush with maternity. Regardless of what society would believe of her, Rachel was willing to maintain her kid. For Rachel it would be an flight from her present life. This babe is merely what Rachel needed, person she could love and care for, person that was portion of her.

After Rachel discovered that she wasn ’ t pregnant but really had a tumour, she took ‘ her ’ life into ‘ her ’ custodies. Until so it had been partly or about to the full controlled by her female parent, but things were merely about to alter. Life had to alter for Rachel. The whole construct of life in the same little town

, with the same people was acquiring to her. Rachel was watching everyone else turn up, except herself. She hardly recognized pupils she had taught in class one because they had evidently changed. However, her pupils recognized her, same old Miss Cameron! That’s precisely why things were acquiring out of manus. Rachel was acquiring older and nil was altering. That’s why she decided to travel, because it was clip. For one time, Rachel did non see her mother’s suggestion to remain in Manawaka. She insisted on go forthing and that would be the concluding say. A new metropolis would convey a new occupation, new friends, and hopefully, a whole new life style.

In A Jest of God, the reader is guided through Rachel ’ s job throughout the novel as the secret plan unfolds. The reader merely finds out how Rachel intends to cover with her quandary at the terminal of the book. In The Book of Eve the novel begins with ‘ the ’ drastic alteration and we get to populate through Eva ’ s different life style with her. Every so frequently she mentions what caused her to go forth, and so we are non informed all at one time of her grounds for go forthing, but bit by bit throughout the narrative.

In The Book of Eve, Eva is acquiring defeated because her ill hubby is handling her as a retainer. Eva finds herself following a really rigorous life style due to Burt and she hence runs off. She runs non merely from the servitude of nursing Burt, but besides from running the house, shopping, cleaning up and that dull modus operandi. It ’ s really rather selfish of Eva to go forth Burt after being devoted to him for 40 old ages, nevertheless, she had to move rapidly because her life was easy being consumed.

Eva has changed in order to suit to her demands. In this instance, her demands are nice and simple. What Eva needs is purdah ; she needs clip to be with herself. Now that Burt is no longer a load to her, she can take her ain life and do her ain determinations without the changeless concern of his torment.

Due to Eve ’ s self-generated going from place, she had to get down a new manner of life. Now Eva is non as financially stable as she was with Burt, yet she still manages. She deprives herself of some things that would ’ ve been indispensable to her in any other state of affairs, in order to salvage money. She eats soups and other nutrients that are cheaper, but non needfully healthier for her. Eva declines money that her boy Neil offers to her. Since Eva was the 1 to go forth Burt, she feels that it ’ s in her best involvement non to depend on any money from him or from her boy. If Eva did have any contributions from her boy, it would be as if she had lost her conflict. If she accepted them, it would be like stating that yes she couldn ’ t back up herself. One of Eve ’ s pursuits was to be able to take attention of herself and hence she was non susceptible to any offerings.

All the agony and conserving that Eva goes through is fundamentally to turn out non merely to others, but chiefly to herself, that she doesn ’ Ts have to set up with other people ’ s jobs. In this instance, since the job is her hubby, it makes it that much more hard to keep herself from returning place. Eva must hold complete dedication to herself and to her ends to let for such hardhearted behavior towards others.

Eva is better off in the sense that she has her purdah, yet she still has friends. Not merely does Eva hold friends, but she besides still has a sex life. Leaving Burt did non intend Eva was now traveling to go a cipher, and she made sure of that. Over the class of the novel, Eva did alter well. Change isn ’ t perchance the best word, but instead acknowledgment. The most of import result of Eve ’ s flight was detecting more about herself. Had she non been so improbably brave to go forth Burt, she wouldn ’ Ts have been able to larn from her life experiences.

When comparing Rachel ’ s character to Eve ’ s, it ’ s pathetic to presume they were under the same fortunes. Eve ’ s life and Rachel ’ s were two wholly different sagas. However when earnestly thought out, they are both prosecuting the same thing. Both adult females were so fighting to accomplish their ain wants and needs when certainly these demands were in struggle with other household members.

Life is like a film. When the film comes to the terminal, it ’ s rewound and everything starts all over once more. Every twenty-four hours in life can be compared to a film rather easy. Day after twenty-four hours, the same everyday tends to happen. Whether or non one wants to modify that modus operandi, is based on their strength, bravery, finding and physical and mental capacity.

Bibliography

Beresford-Howe, Constance. The Book of Eve, Toronto: McClelland and Stewart Inc. , 1966

Laurence, Margaret. A Jest of God, Toronto: McClelland and Stewart Inc. , 1989

Walker, Alice. The Color Purple, New York City: Washington Square Press, 1988

Pic Microcontroller Detail Document

Introduction

PIC controllers are a family of small risk controllers used in embedded applications. PIC controllers are produced by the company „Microchip“ Literature can be obtained from the Microchip web site (www.icrochip.com). The growth of the 8-bit MCU market share is a testament to the PICmicro MCUs ability to meet the needs of many. This growth has made the PICmicro architecture one of the top three architectures available in the general market today. This growth was fueled by the Microchip vision of the benefits of a low-cost OTP solution. Some of the benefits for the customer include: PICmicro devices are grouped by the size of their Instruction Word. The three current PICmicro families are:

  1. Base-Line: 12-bit Instruction Word length

  2. Mid-Range: 14-bit Instruction Word length

  3. High-End: 16-bit Instruction Word length

This manual focuses on the Mid-Range devices, which are also referred to as the PIC16Cxxx MCU family. The operation of the PIC16CXXX MCU family architecture and peripheral modules is explained but does not cover the specifics of each device. Therefore, it is not intended to replace the device datasheets but complements them. In other words, this guide supplies the general details and operation of the PICmicro architecture and peripheral modules, while the datasheets give specific details such as device memory mapping. Initialization examples are given throughout this manual.

These examples sometimes need to be written as device-specific as opposed to family generic, though they are valid for most other devices. Some modifications may be required for devices with variations in register file mappings.

Device Structure

Each part of a device can be placed into one of three groups:

  1. Core

  2. Peripherals

  3. Special Features

The core pertains to the basic features that are required to make the device operate:

  1. Device Oscillator

  2. Reset logic

  3. CPU (Central Processing Unit) operation

  4. ALU (Arithmetic Logical Unit) operation

  5. Device memory map organization

  6. Interrupt operation Revision

  7. Instruction set Revision Peripherals are the features that add a differentiation from a microprocessor.

These ease in interfacing to the external world (such as general-purpose I/O, LCD drivers, A/D inputs, and PWM outputs), and internal tasks such as keeping different time bases (such as timers).

The peripherals that are discussed are:

  1. General-purpose I/O

  2. Timer0

  3. Timer1

  4. Timer2

  5. Capture, Compare, and PWM (CCP)

  6. Synchronous Serial Port (SSP)

  7. Basic Synchronous Serial Port (SSP)

  8. Master Synchronous Serial Port (MSSP)

  9. USART (SCI)

  10. Voltage References

  11. Comparators

  12. 8-bit Analog to Digital (A/D)

  13. Basic 8-bit Analog to Digital (A/D)

  14. 10-bit Analog to Digital (A/D)

  15. Slope Analog to Digital (A/D) w/ Thermister

  16. Liquid Crystal Display (LCD) Drivers

  17. Parallel Slave Port (PSP)

Special features are the unique features that help to do one or more of the following things: -Decrease system cost – Increase system reliability – Increase design flexibility The Mid-Range PICmicro MCUs offer several features that help achieve these goals:

  1. Device Configuration bits

  2. On-chip Power-on Reset (POR)

  3. Brown-out Reset (BOR) logic

  4. Watchdog Timer

  5. Low power mode (Sleep)

  6. Internal RC device oscillator

  7. In-Circuit Serial Programming™ (ICSP™) Revision “DS31028A”

  8. Architecture

The high performance of the PICmicro™ devices can be attributed to a number of architectural features commonly found in RISC microprocessors: ¦ Harvard architecture ¦ Long Word Instructions ¦ Single Word Instructions ¦ Single Cycle Instructions ¦ Instruction Pipelining ¦ Reduced Instruction Set ¦ Register File Architecture ¦ Orthogonal (Symmetric) Instructions Harvard Architecture: Harvard architecture has the program memory and data memory as separate memories and are accessed from separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus.

To execute an instruction, a von Neumann machine must make one or more (generally more) accesses across the 8-bit bus to fetch the instruction. Then data may need to be fetched, operated on, and possibly written. As can be seen from this description, that bus can be extremely busy. While with a Harvard architecture, the instruction is fetched in a single instruction cycle (all 14-bits). While the program memory is being accessed, the data memory is on an independent bus and can be read and written. These separated buses allow one instruction to execute while the next instruction is fetched.

Long Word Instructions: Long word instructions have a wider (more bits) instruction bus than the 8-bit Data Memory Bus. This is possible because the two buses are separate. This further allows instructions to be sized differently than the 8-bit wide data word which allows more efficient use of the program memory since the program memory width is optimized to the architectural requirements.

Single Word Instructions: Single Word instruction opcodes are 14-bits wide making it possible to have all single-word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. With single-word instructions, the number of words of program memory locations equals the number of instructions for the device. This means that all locations are valid instructions. Typically in the von Neumann architecture, most instructions are multi-byte. In general, a device with 4-KBytes of program memory would allow approximately 2K of instructions.

This 2:1 ratio is generalized and dependent on the application code. Since each instruction may take multiple bytes, there is no assurance that each location is a valid instruction. Instruction Pipeline: The instruction pipeline is a two-stage pipeline which overlaps the fetch and execution of instructions. The fetch of the instruction takes one TCY, while the execution takes another TCY. However, due to the overlap of the fetch of current instruction and execution of previous instruction, an instruction is fetched and another instruction is executed every single TCY.

Single Cycle Instructions: With the Program Memory bus being 14-bits wide, the entire instruction is fetched in a single machine cycle (TCY). The instruction contains all the information required and is executed in a single cycle. There may be a one-cycle delay in execution if the result of the instruction modified the contents of the Program Counter. This requires the pipeline to be flushed and a new instruction to be fetched. Reduced Instruction Set: (RISC) When an instruction set is well designed and highly orthogonal (symmetric), fewer instructions are required to perform all needed tasks.

With fewer instructions, the whole set can be more rapidly learned. Register File Architecture: The register files/data memory can be directly or indirectly addressed. All special function registers, including the program counter, are mapped in the data memory. Orthogonal (Symmetric) Instructions: Orthogonal instructions make it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of “special instructions” make programming simple yet efficient. In addition, the learning curve is reduced significantly.

The mid-range instruction set uses only two non-register oriented instructions, which are used for two of the core features. One is the SLEEP instruction which places the device into the lowest power use mode. The other is the CLRWDT instruction which verifies the chip is operating properly by preventing the on-chip Watchdog Timer (WDT) from overflowing and resetting the device.

General Mid-range PICmicro Block Diagram

Memory Organisation

There are two memory blocks, program memory, and data memory. Each block has its own bus so that access to each block can occur during the same oscillator cycle. The data memory can further be broken down into General Purpose RAM and the Special Function Registers (SFRs). Mid-Range MCU devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space.

The width of the program memory bus (instruction word) is 14-bits. Since all instructions are a single word, a device with an 8K x 14 program memory has space for 8K of instructions. This makes it much easier to determine if a device has sufficient program memory for the desired application. This program memory space is divided into four pages of 2K words each (0h – 7FFh, 800h -FFFh, 1000h – 17FFh, and 1800h – 1FFFh). The figure shows the program memory map as well as the 8 level deep hardware stack. Depending on the device, only a portion of this memory may be implemented.

Please refer to the device datasheet for the available memory. To jump between the program memory pages, the high bits of the Program Counter (PC) must be modified. This is done by writing the desired value into an SFR called PCLATH (Program Counter Latch High). If sequential instructions are executed, the program counter will cross the page boundaries without any user intervention. For devices that have less than 8K words, accessing a location above the physically implemented address will cause a wraparound. That is, in a 4K-word device accessing 17FFh actually addresses 7FFh. 2K-word devices (or less) don not require paging.

Reset Vector

On any device, a reset forces the Program Counter (PC) to address 0h. We call this address the “Reset Vector Address” since this is the address that program execution will branch to when a device reset occurs. Any reset will also clear the contents of the PCLATH register. This means that any branch at the Reset Vector Address (0h) will jump to that location in PAGE0 of the program memory.

Interrupt Vector

When an interrupt is acknowledged the PC is forced to address 0004h. We call this the “Interrupt Vector Address”. When the PC is forced to the interrupt vector, the PCLATH register is not modified. Once in the service interrupt routine (ISR), this means that before any write to the PC, the PCLATH register should be written with the value that will specify the desired location in program memory. Before the PCLATH register is modified by the Interrupt Service Routine (ISR) the contents of the PCLATH may need to be saved, so it can be restored before returning from the ISR.

Stack The stack allows a combination of up to 8 program calls and interrupts to occur. The stack contains the return address from this branch in program execution. Mid-Range MCU devices have an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed.

After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).

Special Function Registers (SFR)

The SFRs are used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM.

The SFRs can be classified into two sets, those associated with the “core” function and those related to the peripheral functions. All Mid-Range MCU devices have banked memory in the SFR area. Switching between these banks requires the RP0 and RP1 bits in the STATUS register to be configured for the desired bank. Some SFRs are initialized by a Power-on Reset and other resets, while other SFRs are unaffected. Banking The data memory is partitioned into four banks. Each bank contains General Purpose Registers and Special Function Registers.

Switching between these banks requires the RP0 and RP1 bits in the STATUS register to be configured for the desired bank when using direct addressing. The IRP bit in the STATUS register is used for indirect addressing. Each Bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers. All data memory is implemented as static RAM. All Banks may contain special function registers. Some “high use” special function registers from Bank0 are mirrored in the other banks for code reduction and quicker access.

Through the evolution of the products, there are a few variations in the layout of the Data Memory. The data memory organization that will be the standard for all new devices is shown in the Figure. This Memory map has the last 16-bytes mapped across all memory banks. This is to reduce the software overhead for context switching. The registers in bold will be in every device. The other registers are peripheral dependent.

Not every peripheral’s registers are shown, because some file addresses have a different register from those shown. As with all the figures, tables, and specifications presented in this reference guide, verify the details with the device-specific data sheet. Register file map: The following map shows the register file memory map of some 18-pin devices. (Unimplemented registers will read as ‘0’)

Instruction Set

The Central Processing Unit (CPU) is responsible for using the information in the program memory (instructions) to control the operation of the device. Many of these instructions operate on data memory. To operate on data memory, the Arithmetic Logical Unit (ALU) is required. In addition to performing arithmetical and logical operations, the ALU controls status bits (which are found in the STATUS register).

The result of some instructions force status bits to a value depending on the state of the result. The machine codes that the CPU recognizes are show (as well as the instruction mnemonics that the MPASM uses to generate these codes). Mid-Range MCU Instruction Set.

The Integrated Development Environment (IDE)

The core set of development tools operate under the IDE umbrella, called MPLAB.

This gives a consistent look and feels to all the development tools so that minimal learning of the new tool interface is required. The MPLAB IDE integrates all the following aspects of development:

  • Source code editing

  • Project management

  • Machine code generation (from assembly or “C”)

  • Device simulation

  • Device emulation

  • Device programming

This comprehensive tool suite allows the complete development of a project without leaving the MPLAB environment. MPLAB The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market.

MPLAB is a Windows-based application that contains:

  • A full-featured editor

  • Three operating modes – editor – emulator – simulator

  • A project manager

  • Extensive on-line help MPLAB allows you to:

    • Edit your source files. (ASM and C files)

    • One-touch assemble (or compile) and download to PIC16/17 tools

    • Debug using: – source files – absolute listing file – program memory

    • Run up to four emulators on the same PC

    • Run or Single-step – program memory – source file – absolute listing Microchip’s simulator, MPLAB-SIM, operates under the same platform as the PICMASTER emulator.

This allows the user to learn a single toolset that functions equivalently for both the simulator and the full-featured emulator. de MPLAB Software Language Support To make the device operate as desired in the application, a software program needs to be written for the microcontroller. This software program needs to be written in one of the programming languages for the device.

Currently, MPLAB supports two of Microchip’s language products:

  • Microchip Assembler (MPASM)

  • Microchip ‘C’ Compiler (MPLAB-C) Assembler (MPASM)

The MPASM Universal Macro Assembler is a PC-hosted symbolic assembler. It supports all Microchip microcontroller families. MPASM offers full-featured Macro capabilities, conditional assembly, and several sources and listing formats. It generates various object code formats to support Microchip’s development tools as well as third party programmers.

Provides translation of Assembler source code to object code for all Microchip microcontrollers. Macro assembly capability. Produces all the files (Object, Listing, Symbol, and special) required for symbolic debug with Microchip’s emulator systems. Supports Hex (default), Decimal and Octal source, and listing formats. MPASM provides a rich directive language to support the programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable. C Compiler (MPLAB-C) The MPLAB-C is a complete ‘C’ compiler for Microchip’s PICmicro family of microcontrollers.

For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display, Watch windows, and File register windows.

MPLINK Linker

MPLINK is a linker for the Microchip C compiler, MPLAB-C, and the Microchip relocatable assembler, MPASM. MPLINK allows you to produce modular, re-usable code with MPLAB-C and MPASM. Control over the linking process is accomplished through a linker “script” file and with command-line options. MPLINK ensures that all symbolic references are resolved and that code and data fit into the available PICmicro device.

MPLINK combines multiple input object modules generated by MPLAB-C or MPASM, into a single executable file. The actual addresses of data and the location of functions will be assigned when MPLINK is executed. This means that you will instruct MPLINK to place code and data somewhere within the named regions of memory, not to specific physical locations. Once the linker knows about the ROM and RAM memory regions available in the target PICmicro device and it analyzes all the input files, it will try to fit the application’s routines into ROM and assign it’s data variables into available RAM.

If there is too much code or too many variables to fit, MPLINK will give an error. MPLINK also provides flexibility for specifying that certain blocks of data memory are reusable, so that different routines (which never call each other and don’t depend on this data to be retained between execution) can share limited RAM space.

MPLIB Librarian MPLIB is a librarian for use with COFF object modules created using either MPASM v2. 0, MPASMWIN v2. 0, or MPLAB-C v2. 0 or later. MPLIB manages the creation and modification of library files. A library file is a collection of object modules that are stored in a single file. Libraries make linking easier. Since library files can contain many object files, the name of a library file can be used instead of the names of many separate objects when linking. Libraries help keep code small.

Since a linker only uses the required object files contained in a library, not all object files which are contained in the library necessarily wind up in the linker’s output module. Libraries make projects more maintainable. If a library is included in a project, the addition or removal of calls to that library will not require a change to the link process. Libraries help convey the purpose of a group of object modules. Since libraries can group together several related object modules, the purpose of a library file is usually more understandable that the purpose of its individual object modules.

For example, the purpose of a file named “math. lib” is more apparent that the purpose of ‘power. o’, ‘ceiling. o’, and ‘floor. o’. MPLAB-SIM Simulator Software The software simulator is a no-cost tool with which to evaluate Microchip’s products and designs. The use of the simulator greatly helps debug software, particularly algorithms. Depending on the complexity of a design project a time/cost-benefit should be looked at comparing the simulator with an emulator.

For projects that have multiple engineers in the development, the simulator in conjunction with an emulator can keep costs down and will allow speedy debug of the tough problems. MPLAB-SIM Simulator simulates the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/output radix can be set by the user and the execution can be performed in; single step, execute until the break, or in a trace mode.

MPLAB-SIM supports symbolic debugging using MPLAB-C, and MPASM. The Software Simulator offers the low-cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.

Carbon-offset Trips

Bill is required to enter “Yes” in Column G for any row where the total daily expenses are $100.00 or higher. To accomplish this, he can select the corresponding cell in Column G and type “Yes”. If the daily expenses are less than $100.00, Bill should leave Column G empty for that row. Additionally, Bill has future aspirations of expanding his business and aims to hire one or two employees within a few weeks.

Bill should take into account networking options for the new employees who will be working in a spare room in his house. There are various methods for organizing computers in networks, such as Workup, Domain, and Homegroups.

Each of these options – Workup, Domain, and Homegroups – has its own advantages and disadvantages that should be clarified to Bill. In conclusion, a recommendation should be given regarding the network configuration that Bill should establish. Additionally, an explanation of the necessary hardware for this setup should be provided.

The main difference among them is how the computers and other resources on the networks are managed. Computers running Windows on a network must be part of a workup or a domain. Computers running Windows on home networks can also be part of a home group, but it’s not required. Computers on home networks are usually part of a workup and possibly a homegrown, and computers on workplace networks are usually part of a domain. In a workup: All computers are peers; no computer has control over another computer. Each computer has a set of user accounts.

To access any computer in the workup, an account on that computer is required. Typically, there are no more than twenty computers and no password protection for the workup. All computers must be connected to the same local network or subnet. In a Domain, network administrators utilize servers to manage security and permissions for all computers within the domain. This simplifies the process of implementing changes as they can be automatically applied to all computers. When accessing the domain, domain users are prompted to provide a password or other credentials each time.

By having a user account on the domain, you can conveniently log in to any computer on the domain without requiring separate accounts for each computer. Nevertheless, network administrators often restrict your capability to modify a computer’s settings to ensure consistency across all computers. A domain can encompass multiple computers across diverse local networks. In the scenario of a Homegrown group comprising Windows computers and devices, only group members have permission to share content and devices. Other devices on the same network that are not part of the Homegrown group are unable to access these shared resources.

The computers in the Homegrown do not require a username and password for every connection to a shared resource, unlike older operating systems. Both Windows 7 and Windows 8 devices can join the Homegrown network with no limit on the number of computers. I suggest that Bill selects the Workup option because even if he works from home, it is still considered as a business. Workups provide necessary features like file sharing, printer access, and internet connection, although they do not handle the actual setup of sharing on your behalf.

Bill will need to buy Microsoft operating computers for his new employees since all computers must run on Microsoft operating systems. Additionally, with the potential of three business computers in his home and the vulnerability of his business records, it is a good opportunity to advise Bill on establishing a routine plan for safeguarding and defending his network. Here is a list of the top five concerns for network and computer safety and security, along with the recommended actions and software to be implemented if necessary.

Here are five important concerns for safety and security, along with recommendations to address them:

1. Internet and Network Security: This covers mallard and hacking techniques. One recommendation to keep your data safe while browsing is to always use high level SSL encryption.

2. Data Loss by Accidents: This issue is caused by problems with data storage devices. One recommendation to prevent data loss caused by a computer/server crash is to implement a solid backup plan to recover lost data packets in transit.

Data files can be replicated across a remote server and various computers on a network. One potential risk is the misuse of user rights, where individuals with certain privileges may steal company data and sell it to competitors. To prevent this, it is recommended to monitor shared files within workup networks. This monitoring can be done through the administrator computer on the network. Another concern is spamming, which can be carried out by both internal and external hackers. The strategy involves overwhelming the network with bogus data packets. To counteract this, one should exercise caution regarding misleading ads and pop-ups that could result in unintentional downloading of malicious software onto your computer.

Many web browsers include pop-up blockers, and there are also browser plug-ins that can be used to remove ads. Another way to prevent unauthorized access on individual computers is by programming them to automatically lock after a certain period of inactivity. This feature is found in Windows operating systems, where users can set passwords for each account and configure the settings to require the password when the screen saver is turned off. Additionally, users have the option to shorten the time before the screen saver activates.